Talk:Program counter

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"program counter" is a non-standard misnomer

This thing doesn't count programs. It counts instructions.

Wait, it doesn't count either. It jumps around in response to various events and instructions. IA-32 examples: call, ret, int, syscall, sysenter, sysret, iret...

So it's not a counter. It's a pointer.

Well gee. That must be why Intel called it the instruction pointer in their documentation.

OK, never mind the most popular CPU architecture. What about the Mac or Xbox/360? There we have the next instruction pointer register, and current instruction pointer as a concept in the documentation.

24.110.60.225 00:46, 1 January 2006 (UTC)[reply]

Yes, it counts :-)

The vast majority of instruction fetches are from the next memory location after the previously fetched instruction.

Random-access jumps or branches to other locations are relatively infrequent by comparison.

The PC is a pointer, true, and also a counter

TheAMmollusc (talk) 11:47, 20 October 2008 (UTC)[reply]

Von Neumann himself used the term "Program Counter." I think "Instruction Pointer" is a non-standard misnomer. Whenever I see "IP" in a computer-related context I think of "Internet Protocol" (specifically the "IP address") or "Intellectual Property" before I think of Intel's non-standard misnomer. When I see "PC" in a computer-related context I think of "Personal Computer" and then "Program Counter." "EIP" looks like a sound someone makes when they step on something sharp or slimy, and "RIP" means I'll soon be able to say "RIP" to the x86 that only exists today because of the Datapoint 2200, IBM and Microsoft. I just can't wait for Ivy Bridge: I'd be able to boot DOS twice as fast! — "Windows n. (Win-doze): A 64 bit tweak of a 32 bit extension to a 16 bit user interface for an 8 bit operating system based on a 4 bit architecture from a 2 bit company that can't stand 1 bit of competition." 69.54.60.34 (talk) 05:26, 26 February 2011 (UTC)[reply]

Hey, there's a lot of truth to that. You got me laughing as hard as I have at any joke told on TV at 11:30pm in a long time, thanks. Seems like a perfect example of Not Invented Here syndrome. Trouble is, oftentimes the we set the standards crowd uses superior business strategy to make their version better known and more widely adopted than the inventor's, leaving it up to neutral Wikipedia editors to sort through the confusion. I'll update the article to provide some references and clarify things for people like the student below. Wbm1058 (talk) 20:25, 21 October 2011 (UTC)[reply]

Page 1-5 (PDF page 16) of the Intel iAPX88 Book] says Figure 1-9 shows two 16-bit control registers. First is the IP or instruction pointer which points to the next instruction the bus interface unit will fetch. (The instruction pointer is similar to a Program Counter used in other microprocessors, except that the IP points to the next instruction being fetched, whereas the traditional program counter points to the next instruction to be executed). Intel themselves used the term Program Counter in their 8008 and 8080 processors. BTW, PowerPC calls it a Next Instruction Address Register which is a much better term because "Instruction Pointer" can refer to anything holding an instruction address! — Preceding unsigned comment added by 69.54.62.196 (talk) 05:10, 17 September 2012 (UTC)[reply]

It would be more intuitive (imo) if it were called instruction pointer, because it points to the fact that we are talking about an address in memory which holds the next or current instruction (depending on the architecture) and is not counting the amount of instructions that have been executed. The value can also be overwritten by (conditional) jump instruction which makes it even more confusing when we talk about a counter that doesn't really count at all. — Kavuldra (talk) 15:08, 21 July 2019 (UTC)[reply]

instruction pointer disambiguation

I have been reading a bit in my course book about computer hardware and found the following information:

8086/8088 processors have a 16 bit data bus and a 20 bit address bus, so two registers are needed to contain an address: a segment register and an offset register. The memory address can be obtained by bit-shifting the segment register by four bits to the left and performing a summation with the offset register. The memory a program used is seperated into segments. The segment containing the code is called the code segment, and it's segment register is named CS. It's offset register is named IP or instruction pointer.

This information should be added in a page on instruction pointer and a disambiguation page should be made.

--Bernard François 11:39, 6 March 2006 (UTC)[reply]

No, no, please don't. We don't need a content fork. PC and IP are truly two different terms for the same fundamental concept. If you understand this you should LOL at the joke in the above section. This is a related discussion so I'm making it a subtopic under the above. Wbm1058 (talk) 20:25, 21 October 2011 (UTC)[reply]

POV section: "All-pervasive nature of the program counter"

This is horribly unencyclopaedic in its tone, somewhere in-between OR and a POV diatribe. I'm tempted to get rid of it, because it's not particularly informative. Any thoughts? Oli Filth^{(talk|contribs)} 01:08, 25 April 2012 (UTC)[reply]

I thought my version was a vast improvement in terms of this exact problem. In particular, it went from exploring the state-of-mind of the programmer, to merely discussing the implications of the sequential-execution model. I do not see why you reverted to the previous version to attach {{POV}}. Spike-from-NH (talk) 01:43, 25 April 2012 (UTC)[reply]

Oh, that was completely unintentional, I have no idea how that occurred. Reverted now. Oli Filth^{(talk|contribs)} 13:17, 25 April 2012 (UTC)[reply]

Whew! Thank you for the clarification. Spike-from-NH (talk) 17:39, 25 April 2012 (UTC)[reply]

integrated development environment

The article currently says

"In an integrated development environment, the programmer may write sequences of instructions to respond to events without specifying an overall sequence for the program."

That description sounds more like the description of event-driven programming to me. How the IDE is relevant here?

It seems as irrelevant to me as pointing out that

"While wearing shoes, the programmer may write sequences of instructions to respond to events without specifying an overall sequence for the program."

It's technically true that people often use an IDE (and wear shoes) while doing event-driven programming, but my understanding is that people find an IDE (and shoes) just as useful for programming purely sequential paradigms, and both purely sequential and event-driven software can be written without an IDE (and without shoes). I deleted the phrase "integrated development environment", but now I wonder: Is there a special connection between IDEs and non-sequential programming that I've missed? --DavidCary (talk) 20:28, 2 March 2013 (UTC)[reply]

There is not. The two concepts go together in my limited experience programming after text editors, but your edit makes it more precise.

Regarding the paragraph you added afterward, you need an initial "In" at least for parallelism. And your three links seem inter-related. As your text says they go from the specific to the general, you should pick the one whose generality aligns most closely with "writ[ing] each section of the pipeline without specifying the timing relative to other sections." Spike-from-NH (talk) 02:25, 3 March 2013 (UTC)[reply]

IBM 650-style "next instruction field" as a PC equivalent

This page said

Use of a PC that normally increments assumes that what a computer does is execute a usually linear sequence of instructions. Such a PC (or equivalent hardware that serves the same purpose[8]) is central to the von Neumann architecture. Thus programmers write a sequential control flow even for algorithms that do not have to be sequential.

with reference 8 pointing to The story of Mel - an entertaining story, but really not much of a reference.

If the intent was to refer to the RPC 4000's "next instruction" field in all instructions, with branches having a "branch to" instruction if the branch test succeeds and a "next instruction" field if the test fails, or similar mechanisms in other machines such as the IBM 650, it would be best to do so explicitly, so I changed it to do so.

That mechanism isn't "equivalent" in the sense of sequentially stepping through memory locations containing instructions (except when a branch occurs), but it is "equivalent" in the sense that machines with a PC (and an implied "next instruction" address of "first memory location after the current instruction") both sequentially execute a sequence of instructions. For machines with a PC, that sequence can be thought of as an array; for machines with a "next instruction" field, it could be thought of as a linked list.

As the paragraph in question was discussing sequential execution, the "next instruction" address is "equivalent" in that it doesn't provide any escape from sequential execution; if the intent is to speak only of program counters requiring sequential execution, without anything being said one way or the other about next instruction addresses, then the entire parenthetical note (whether the version before or after my edit) should be removed.

I'm not sure it's best described as "having a PC implies sequential execution"; it's perhaps better described as "sequential execution allows the use of a PC" - it's not as if removing the transistors that store the PC value is sufficient to allow the machine to run code in parallel; it's more like dataflow etc. machines have no place for a PC. Guy Harris (talk) 07:09, 15 April 2015 (UTC)[reply]

Yes; I had challenged your edit on your talk page. Your point is made that PCs don't "imply sequential execution" (and the article goes on to describe alternative concepts in the following section). And I too found "A story of Mel" interesting but not relevant to this discussion.

The section in question discusses what computers "typically" do and how that led to problems, more research, and different architectures. Atypical examples did not lead to any of the above. The word "typically" implies there are counterexamples; regarding listing them, it's unlikely that a reader would come to Program counter to read about computers that didn't use program counters, but if you think so, that should be a separate discussion in the article. At least, the parenthetical remark should be removed. Spike-from-NH (talk) 12:47, 15 April 2015 (UTC)[reply]

Hearing no objection, I removed the remark. Spike-from-NH (talk) 12:50, 21 April 2015 (UTC)[reply]

PC/IP pointing past the current instruction

@Spike-from-NH:, @Mildsunrise::

A recent edit added the claim that "In some architectures, the PC points to the current instruction plus a processor-dependent constant."; that edit was reverted.

The claim was presumably derived from the "Saving from r15" section of this part of the ARM Developer Suite Assembler Guide, which said:

In general, avoid saving from r15 if possible.

If you do save from r15, the value saved is the address of the current instruction, plus an implementation-defined constant. The constant is always the same for a particular processor.

In manuals describing an instruction set, the PC/IP is probably mostly used in a description of the behavior of the idealized processor that all implementations of the instruction set provide. For example, it would be used in descriptions of instructions, e.g.:

JMP [EA] - Jump unconditionally

PC <- [EA]

JSR [R], [EA] - Jump to Subroutine

[R] <- PC

PC <- [EA]

In some instruction sets, including the one whose instructions are described there, when an instruction is executed, the PC/IP points to the instruction following the one being executed, so that 1) the address of that instruction is saved as the return address and 2) when the instruction finishes, the next instruction is fetched from the PC/IP, meaning that the jump instructions cause the next instruction to be fetched from the effective address of the jump instruction. The current x86 manuals seem to show the IP/EIP/RIP working that way, as, with RIP-relative addressing, "An effective address is formed by adding displacement to the 64-bit RIP of the next instruction.", and in the description of the CALL instruction, one step is "Push(IP);", "Push(EIP);", or "Push(RIP);", pushing the address of the next instruction onto the stack.

For others, such as MIPS32, it points to the instruction being executed, so that, to quote the MIPS32 manual:

The address of the instruction that occurs during the next instruction time is determined by assigning a value to PC during an instruction time. If no value is assigned to PC during an instruction time by any pseudocode statement, it is automatically incremented by either 2 (in the case of a 16-bit MIPS16e instruction) or 4 before the next instruction time. A taken branch assigns the target address to the PC during the instruction time of the instruction in the branch delay slot.

and, in the description of the Jump and Link instruction, the first step of the sequence of steps is

GPR[31] <- PC + 8

(+8 = +4+4, with the first +4 skipping over the JAL instruction and the second +4 skipping over the instruction in the delay slot).

The instruction set might make it visible as a general-purpose register; A32 (32-bit ARM), for example makes it visible as r15. What the ARMv7 A-profile manual says is:

PC, the program counter

When executing an ARM instruction, PC reads as the address of the current instruction plus 8.
When executing a Thumb instruction, PC reads as the address of the current instruction plus 4.
Writing an address to PC causes a branch to that address.

So, for 32-bit ARM (the 32-bit instruction set containing ARM instructions), the PC points to the instruction following the next instruction, as instructions are all 4 bytes long. I'm not sure what the case is for Thumb/Thumb-2, as there are both 16-bit and 32-bit instructions. The Branch and Link instruction sets the link register (r14) to PC - 4, backing it up to point to the instruction following the BL instruction.

So, at the instruction set architecture level, while an instruction is being executed, the PC/IP might point to the instruction being executed, to the instruction following the instruction being executed, or somewhere else following the instruction being executed.

At the microarchitecture level, there might not be a set of N transistors that make up "the program counter register" or "the instruction pointer register"; each instruction being executed might, for example, have, associated with it, a PC/IP value appropriate to that instruction, following the rules of the instruction set architecture, and the instruction fetch hardware might have its own register holding the PC/IP value, which it copies into the stuff it hands to the execution hardware.

So the page should perhaps distinguish between "PC/IP as a concept in the description of the instruction set architecture" and its implementation in various microarchitectures. The "Hardware implementation" should discuss only the latter of the two - and not make any claims without reliable sources. That might reduce the contents of that section substantially if the references can't be found, and expand the contents substantially if they can be found. :-) The rest of the article should probably focus on the instruction set architecture PC/IP, and just indicate that it might, during the execution of an instruction, point to the instruction being executed, the next instruction that would be executed if the instruction doesn't cause a transfer of control (or even if it does cause a transfer of control if there's a branch delay slot), or some arbitrary instruction set architecture-defined or implementation-defined place past the instruction being executed. — Preceding unsigned comment added by Guy Harris (talk • contribs)

Thanks; I did not grasp this from the cited page. I've restored a version of the new sentence but moved it (and the other sentence with an exception to the rule) out of the Intro and into Notes. On a further reorganization of the article, I have no opinion. Spike-from-NH (talk) 13:22, 21 October 2019 (UTC)[reply]

I agree; most people reading the article will be thinking of PC in the context of an instruction set. Mildsunrise (talk) 11:30, 22 October 2019 (UTC)[reply]

I removed the Symbol section as not being very relevant here

The Symbol section mostly described symbols used in expressions evaluated by the assembler at assembly time to refer to the address of the current instruction, i.e. the value the program counter would have when the fetch of the instruction in question begins. That strikes me as more relevant to assembly language than to this page. One term used for the address of the current instruction is the "location counter"; see, for example, page 3 of the PDP-7 assembler manual, page 3-8 of the PAL III Symbolic Assembler Programming Manual for the PDP-8, page 3-13 of the PDP-11 MACRO-11 Language Reference Manual, page 3-18 of the VAX-11 MACRO Language Reference Manual, and pages 18-19 of the IBM Operating System/360 Assembler Language manual. It's called the "location assignment counter" for the 1130; see pages 7-8 of the IBM 1130 Assembler Language manual.

The bit about DEC describes, instead, a symbol used to refer to the program counter as an operand fetched (or stored into) by an instruction at run time, for those instruction sets that support this such as the PDP-11 and VAX instruction sets. DEC generally uses . as the symbol for the address of the instruction; see, for example, page 10 of the PDP-7 assembler manual, page 3-8 of the PAL III manual, page 3-13 of the MACRO-11 manual, and page 3-18 of the VAX MACRO manual. The use of . is more relevant to assembly language, juast as for other symbols; the use of PC in operands may be relevant to this page, with a discussion of those instruction sets where the PC can be used in operand specifiers.

IBM tended to use "*" as the symbol. See, for example, pages 4-5 of the IBM 7090/7094 Programming Systems FORTRAN II Assembly Program (FAP) manual (where they don't seem to have a phrase such as "location counter", although, according to page 25, the pseudo-operation to set the counter is LOC), pages 18-19 of the OS/360 assembler manual, and pages 9-10 of the 1130 assembler manual.

As for *-*, that's a convention used by programmers in various IBM assembler languages to indicate to human readers of the code a value that would be set at run time; see, for example, page 5 of the IBM FAP manual. The two *s in the expression refer to the "location counter" value; it may just be that it's a visually-notable pre-defined symbol such that subtracting it from itself 1) produces a result of 0 to use as a placeholder and 2) looks visually distinct - it may not be significant that what you're subtracting from itself is the location counter. That's a convention possibly worthy of note, but more relevant either to the assembly language page or to the pages about the computers where that convention was used. Guy Harris (talk) 23:30, 8 September 2023 (UTC)[reply]

Uses other than control flow?

Has the PC got other uses than direct control flow? Theoretically it could:

Statistics about code execution.
Code block ID partitioning to imply some attribute(s). With memory mapping the same code data could then have alternative meaning.
Provide a magic number just once, by locating the code just right.

Musaran (talk) 06:23, 25 December 2023 (UTC)[reply]

One very common such use is memory references in position-independent code, such as relative branches (the target displacement of which does not have to change if the code is moved to a different address) and data references through the Global Offset Table in position-independent code in a dynamic shared library on most UN*xes.

The first example you give is used in code profiling; one form of code profiling is done by software sampling the PC and keeping a histogram of its value.

In principle the other two examples could be used, but I don't know of any cases where the PC is used in that fashion. Guy Harris (talk) 08:19, 25 December 2023 (UTC)[reply]